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Unformatted text preview: Name: Student No: ELE 312 DIGITAL ELECTRONICS EXAM I (25%) PART B (SOLUTIONS) Q4 Q5 Q6 TOTAL 25 25 25 50 April 6 𝑡ℎ , 2010 Solve 2 questions from Part B, and 4 questions in total (from Part A and B). Good Luck! Q4. (25 pts) A circuit shown in block form below is to be implemented using TTL logic. The specification for the circuit states that the power dissipated must be less than 13W, the maximum delay must be less than 140ns. Which logic families should be used to implement each block in this circuit? Show all steps and clearly explain your reasoning. Family Delay Power I in I out F1 2 ns 10 mW 0.5 mA 20 mA F2 9 ns 2 mW 0.4 mA 4 mA F3 2 ns 4 mW 0.6 mA 20 mA F4 9 ns 10 mW 1.6 mA 16 mA F5 3 ns 20 mW 2 mA 20 mA F6 4 ns 1 mW 0.1 mA 8 mA Q5. (25 pts) Consider the logic circuit shown below. Assume all diodes are identical. 𝑉 𝐶𝐶 = 5 𝑉 𝑉 𝐸𝐸 = 5 𝑉 𝑅 𝐻 = 2 kΩ 𝑅 𝐿 = 2 kΩ 𝑉 𝐷 ( 𝑂𝑁 ) = 0 . 7 𝑉 a) Determine the logic function. b) Sketch the voltage-transfer characteristics (VTC) of this circuit indicating 𝑉 𝑂𝐿 , 𝑉 𝑂𝐻 , 𝑉 𝐼𝐿 and 𝑉 𝐼𝐻 on the graph, where 𝑉 𝐼𝑁𝐴 = 𝑉 𝐼𝑁𝐵 = 𝑉 𝐼𝑁 ....
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- Spring '11
- Average Power, Logic gate, Logic family, output low state