cmos - it is driving 5 similar inverters and the load...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 312 Digital Electronics Take Home Exam Part VI Due: April 28, 2010 CMOS Inverters Q.1. Consider the inverter given in the following figure. M O M L V DD V O V IN K N =K’ N (W/L) N K P =K’ P (W/L) P K’ N = 250 μ A/V 2 K’ P = 100 μ A/V 2 V DD = 5V (W/L) N = 1μm/1μm L P = 1μm V T,N = 1V V T,P = -1V (a) Determine the width (W) of the pMOS transistor to have a symmetric VTC for the inverter. Sketch the VTC. Indicate the V OH , V OL , V IL , and V IH points (You do not need to calculate V IL , and V IH ). (b) Determine the maximum operation frequency of this inverter, assuming that
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: it is driving 5 similar inverters, and the load capacitance is only due to the gate capacitances, where C ox =15fF/ μ m 2 . Assume that the clock signal has 50% duty cycle. (c) Simulate this circuit in Spice and find V OH , V OL , V IL , V IH , and the maximum operation speed. Compare the simulation results with the calculated values in part (a) and (b) Q.2. Implement the following logic function in CMOS....
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online