Unformatted text preview: it is driving 5 similar inverters, and the load capacitance is only due to the gate capacitances, where C ox =15fF/ μ m 2 . Assume that the clock signal has 50% duty cycle. (c) Simulate this circuit in Spice and find V OH , V OL , V IL , V IH , and the maximum operation speed. Compare the simulation results with the calculated values in part (a) and (b) Q.2. Implement the following logic function in CMOS....
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- Spring '11
- Trigraph, Logic gate, CMOS Inverters Q.1