TTL logic - using EWB(or Spice simulations Use the availble...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 312 Digital Electronics Take-Home Exam Part 4 Due: 13/14 April 2010 1 TTL Logic Gates 1) Consider the following TTL circuit. a) Obtain VTC (voltage transfer characteristics) b) Calculate the maximum fanout for high output. c) Calculate the maximum fanout for low output. Assume high noise margin, NM H =1V, and low noise margin NM L =0.3V. V CC 5V Q P Q O R C R B R D V IN R CP Q S 2k 2.4k 100 6k D L Q I V OUT For the transistors: β F =20 β R =0.10 V CE(SAT) =0.2V V BE(FA) =0.7V V BC(RA) =0.7V V BE(SAT) =0.8V For the diode : V D(ON) =0.7V 2) Consider the following standart low power TTL gate. Obtain the voltage transfer characteristics
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: using EWB (or Spice) simulations. Use the availble components available in the simulator’ library. List the important diode and transistor parameters that you have used. (You may connect a very large resistor, e.g., 10 M Ω to the output to observe the turn-on voltage drops over the pn-junctions) V CC 5V Q P Q O R C R B R D V IN R CP Q S 12 k Ω 20 k Ω 500 Ω 40 k Ω D L Q I V OUT...
View Full Document

This note was uploaded on 05/04/2011 for the course ELECTRONIC 312 taught by Professor Umutsezen during the Spring '11 term at Hacettepe Üniversitesi.

Ask a homework question - tutors are online