# spc_tut - GETTING STARTED WITH HSPICE A TUTORIAL Charles R...

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January 29, 1998 1 GETTING STARTED WITH HSPICE – A TUTORIAL Charles R. Kime Dept. of Electrical and Computer Engineering University of Wisconsin – Madison INTRODUCTION A SPICE (HSPICE) simulation has three primary steps: 1) Generating the circuit netlist file, 2) Running the simulation, and 3) Displaying, analyzing, and printing the simulation results. In this tutorial, we will carry out these three steps for an implementation of an Exclusive OR gate made up of four NAND gates. Since this is a digital circuit, digital electronic circuit simulation techniques are used rather then analog techniques used in other elec- tronics courses. Some differences are: 1) Input waveforms: DC, PWL (Piece-Wise Linear) PULSE versus AC, DC, SIN, EXP. 2) Analysis: DC and TRAN vs. OP, AC, FOUR, NOISE, SENS, etc. 3) Circuit Elements: V, F(I-controlled I source), C, R, M(MOSFET), Q(BJT), T(Lossless line), U(Uniform RC line). The EXOR gate will be hierarchical – made of 4 NAND gates – as shown in Figure 1a). The logic and circuit design has been completed. In addition, we have enough of a lay- out to estimate the areas and perimeter of the sources and drains and the capacitive load- ing on the circuit within an IC.

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DEVICE MODEL FILES 2 GETTING STARTED WITH HSPICE – A TUTORIAL DEVICE MODEL FILES You are to establish your own directory and collection of device models for MOSFETS and other devices. 1. Make a directory for SPICE models. Suggested name: spice_models . 2. Open Netscape and go to the ECE 555 Contents and Links page. 3. Open HSPICE Level 13 for 0.6 micron CMOS Process. 4. Save as scn06hp.L13 in your SPICE models directory. FILE GENERATION The netlist file is made up of statements. A SPICE file is case-insensitive except for file names exported to UNIX as in a .include or .lib statement. * in the left column designates a comment. Netlist Structure: Title (Required) Circuit Subcircuit(s) Device Models Analysis Output .end (Required) File Entry for the Example 1. Make a directory for the files for this tutorial. 2. Edit the netlist file design.sp . 3. Enter title . 4. Enter the Exclusive OR circuit made up of NAND subcircuits. Assume that the statement for the NAND subcircuit is: Xi top_in bot_in out NAND The component labels and input and output nodes to appear in the above statement for each gate can be obtained from Figure 1a). Example statement: X1 101 102 103 NAND Note that GND is always node 0 and that we will reserve node 1 for VDD. 5. Enter the subcircuit for the NAND gate. a. Declare the subcircuit by entering: .SUBCKT NAND top_in bot_in out
FILE GENERATION GETTING STARTED WITH HSPICE – A TUTORIAL 3 FIGURE 1-1 Tutorial Circuit a) Logic Design – EXOR: b) Circuit Design – NAND 2: V DD A B X Y out top_in bot_in 4 1 2 101 102 106 OUTPUT 103 104 105 X1 X2 X3 X4 M1 M2 M3 M4 For all MOSFETs: L=0.6u W=1.2u AD=2.88p AS=2.88p c) Simulation Environment – EXOR: EXOR VA VB + + 0 0 00 101 102 106 C1 = 0.01pf VDD = 3.3 V 0 PD=7.2u PS=7.2u 1

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FILE GENERATION 4 GETTING STARTED WITH HSPICE – A TUTORIAL b. Enter each of the four MOSFETs using the node numbers given in Figure 1b). The format for a MOSFET is:
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spc_tut - GETTING STARTED WITH HSPICE A TUTORIAL Charles R...

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