L03-Verilog

# L03-Verilog - Fall 2009 ECE 18-240 Fundamentals of Computer...

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Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 3: Verilog Introduction Don Thomas & William Nace Electrical & Computer Engineering Carnegie Mellon University LEC 3 Fall 09 18-240 LEC3 — 18-240: Where are we. ..? 1 Handout: Lec3; HW1 is (still) out on Blackboard Labs and recitations start this week. 2 Week Date Lecture Reading Lab HW 1 8/25 L0 Introduction, Comb. Logic Chapter1 (optional) & Chapter2 (optional) No Lab 8/27 L1 Boolean Algebra Ch4.1~4.2 8/28 No Friday recitations 2 9/1 L2 Karnaugh Maps Ch4.3 Lab 0 HW1 9/3 L3 Verilog HDL and simulation Ch5.1 and Ch5.4 9/4 Recitation 3 9/8 L4 Logic Minimization (Q-M Algorithm) Ch4.3~4.4 Lab 1A 9/10 L5 Structured Logic Implementation 9/11 Recitation: HW1 and Quiz 4 9/15 L6 Synthesizable Verilog Chapter 6 Lab 1B HW2 9/17 L7 Comb. Logic Wrap-up Chapter 6 9/18 Recitation: Lab Quiz 5 9/22 L8 Numbers and Arithmetic Chapter 2; HW3 Out Lab 2A 9/24 L9 Flip-fops and FSMs Chapter 7.1~7.8 9/25 Recitation: HW2 and Quiz

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Fall 09 18-240 L3 — Verilog Introduction What you know so far Many ways to represent combinational circuits (Boolean algebra, minterms, maxterms…) and simplify them (Kmap) What you don ʼ t know Industrial-strength representation tools: Verilog Hardware Description Language (HDL) Everyone on the planet speciFes large designs with HDLs Today: Structural Verilog and Simulation Verilog: gates, wires and hierarchy A little on how the simulator works How to put a circuit together and test it before building it 3 Fall 09 18-240 L3 — 1970: Intel 4004, first single chip CPU 4-bit processor for a calculator. 2,300 transistors 16-pin DIP package 740kHz (eight clock cycles per CPU cycle of 10.8 microseconds) ~100K OPs per second You can download the actual schematic from http:// www.intel.com/museum/ archives/ pdf/4004_schematic.pdf [from Molecular Expressions] 4
Fall 09 18-240 L3 — 64-bit processor 1.9 billion transistors 2.1 GHz, issue up to 5 instructions per cycle, per core (ie, x 4 cores) > 20 MByte of cache!! In ~30 years, about 100,000 fold growth in transistor count and performance! 2008: Intel Quadcore Xeon (Dunnington) 5 http://en.wikipedia.org/wiki/Xeon Fall 09 18-240 L3 — How to deal with this complexity? … Hardware Description Languages They ʼ re a fact of life in the computer engineering lane Need to be able to specify complex designs communicate with others in your design group … and to simulate their behavior yes, it ʼ s what I want to build … and to synthesize (automatically design) portions of it have an error-free path to implementation Hardware Description Languages Serve in this role Many similarly featured HDLs (e.g., VHDL, iHDL, . ....) if you learn one, it is not hard to learn another mapping between languages is mechanical, especially for the commonly used subset Verilog for us (the most popular in practice) 6

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Fall 09 18-240 L3 — Verilog Descriptions: Top-Level View 4 standard pieces A top module to enclose the whole description.
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## L03-Verilog - Fall 2009 ECE 18-240 Fundamentals of Computer...

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