L05-MuxesPALs

# L05-MuxesPALs - Fall 2009 ECE 18-240 Fundamentals of...

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Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 5: Structured Logic Realization Carnegie Mellon University LEC 5 Fall-09 18-240 LEC5 — 18-240: Where are we. ..? 1 Handout: Lec5 HW1 due in your recit section. Short QUIZ in your recit, too Lab1 starts this week, part 1A this week. 2 Week Date Lecture Reading Lab HW 1 8/25 L0 Introduction, Comb. Logic Chapter1 (optional) & Chapter2 (optional) No Lab 8/27 L1 Boolean Algebra Ch4.1~4.2 8/28 No Friday recitations 2 9/1 L2 Karnaugh Maps Ch4.3 Lab 0 HW1 9/3 L3 Verilog HDL and simulation Ch5.1 and Ch5.4 9/4 Recitation 3 9/8 L4 Logic Minimization (Q-M Algorithm) Ch4.3~4.4 Lab 1A 9/10 L5 Structured Logic Implementation 9/11 Recitation: HW1 and Quiz 4 9/15 L6 Synthesizable Verilog Chapter 6 Lab 1B HW2 9/17 L7 Comb. Logic Wrap-up Chapter 6 9/18 Recitation: Lab Quiz 5 9/22 L8 Numbers and Arithmetic Chapter 2; HW3 Out Lab 2A 9/24 L9 Flip-fops and FSMs Chapter 7.1~7.8

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Fall-09 18-240 L5 — What you know so far… Kmaps and 2-level SOP for smallish (random) logic functions QM can be used too — in a computer tool What you don’t know… Other ways to approach large designs Partitioning a design into smaller, more manageable chunks Using pre-designed components as parts of larger designs as configurable devices Today Multiplexors (and factoring big Boolean expressions) Demultiplexors/Decoders (and more factoring. ..) Array-style logic options Today: Structured Logic Realization 3 Fall-09 18-240 L5 — Multiplexors 4
Fall-09 18-240 L5 — Multiplexors (aka Mux) Consider 1-bit 2:1 Multiplexor Can write Boolean eqn for output Generate truth table 0 1 Z I 0 I 1 Sel A 5 A I 1 I 0 Z 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 Fall-09 18-240 L5 — Multiplexors: Drawing Conventions I0 I1 I2 I3 Minimalist: for cluttered diagrams, this simpliFes S 2 I0 I1 I2 I3 S1 S0 Z Plain 4:1 mux I0 I1 I2 I3 Z S1 S0 Artsy 4:1 mux Specifications Size: how many different inputs (2 n ) can be selected? Bit-Width: how many bits wide is each input? In general 2 n data inputs, n select lines (also called control inputs), 1 output is a 2 n :1 or “2 n by 1” mux Select lines form binary index of data input to send to output 6

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Multiplexors: Example usage A shared “function unit”, in this case, a binary adder. Depending on Sa and Sb, we can add: A0+B0, A0+B1, A1+B0, or A1+B1 Let ʼ s consider the gate level implementation of the mux 7 2:1 M U X A0 A1 S a 2:1 M U X B0 B1 S b SUM A B Fall-09 18-240 L5 — Multiplexors: Gate-level • Always look alike — very stylized gate-level form Gate Level Implementation of 4:1 Mux Gate Level Implementation of 2:1 Mux Z = A' I 0 + A I 1 A B I0 I1 I2 I3 Z A I0 I1 Z Warning: Don ʼ t get too hung up on this. They look different when implemented directly in transistors. A mux is a mux unless you are the person actually building the mux. 8
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## This note was uploaded on 05/10/2011 for the course ECE 18240 taught by Professor Hoe during the Fall '08 term at Carnegie Mellon.

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L05-MuxesPALs - Fall 2009 ECE 18-240 Fundamentals of...

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