L06-CombSynVlog

L06-CombSynVlog - Fall 2009 ECE 18-240 Fundamentals of...

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18240, Fundamentals of Computer Engineering — 1 Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 6: Synthesizable Verilog (For Combinational Logic) Don Thomas & William Nace Electrical & Computer Engineering Carnegie Mellon University LEC 6 Fall-09 18-240 LEC6 — 2 18-240: Where are we. ..? 1 Handout: Lec6 HW2 is out now on Bb. Lab1 continues this week, part 1B this week.
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18240, Fundamentals of Computer Engineering — 2 Fall-09 18-240 LEC6 — 3 Synthesizable Verilog (Comb. Logic) What you know so far… Using gate level Verilog for specification and simulation Using limited behavioral modeling for the testbench What you don’t know Being able to write synthesizable descriptions and work with a synthesis tool is the prevalent mode of ASIC design. Behavioral modeling — always, initial, if-then-else, loops, case, #, @, wait, … How to write Verilog for synthesizing comb. logic designs How it’s like and unlike writing C Readings DDPP: Chapter 5.4 Verilog book (5th ed): Chapter 1.2, 2.3.1-2.3.4, 3.1, 8.1-2 Verilog Documentation on Blackboard Fall-09 18-240 LEC6 — 4 What do we mean by “Synthesis”? Logic synthesis tool A program that “designs” logic from (more) abstract descriptions of the logic takes constraints (e.g. size, speed) uses a library (e.g. 3-input gates) How? You write an “abstract” Verilog description of the logic The synthesis tool provides “optimized” implementations Verilog blah blah blah or … synthesis library constraints
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18240, Fundamentals of Computer Engineering — 3 Fall-09 18-240 LEC6 — 5 FPGA Synthesis in the Labs mumble mumble blah blah Synthesizable Verilog Synthesis Technology Mapping LE 1 LE 2 Place and Route gates, gates, gates, … Logic Blocks in Xilinx Chip “Abstract” logic “Mapped” logic A not-so-powerful synthesis example Synthesis from gate-level (ie, structural ) models You type the left, synthesis gives you the gates It used a different library than you did. (2-input gates only) It simplified the logic for you if you didn’t do a good job One description suffices for a variety of alternate implementations! ... but this still requires you to know the implementation at the gate level — this is not an “abstract” description. module stuff (output f, input a, b, c); and A (a1, a, b, c), B (a2, a, ~b, ~c), C (a3, ~a, o1); or D (o1, b, c), E (f, a1, a2, a3); endmodule a b c f a possible outcome This is still a lot of work for something so simple
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18240, Fundamentals of Computer Engineering — 4 module stuff (output f, input a, b, c); and A (a1, a, b, c), B (a2, a, ~b, ~c), C (a3, ~a, o1); or D (o1, b, c), E (f, a1, a2, a3); endmodule A better example (New idea: Continuous assign ) Still like Boolean logic. What about very complicated combinational functions? module stuff (output f, input a, b, c); wire t; assign t= (b | c) assign f = (a?~t:t) | (b&c) endmodule Better yet. Let me write what I am really thinking. The tools Fgure out minimization and gate mapping module stuff (output f, input a, b, c); assign f =(a&b&c)|(a&(~b)&(~c))|((~a)&(b|c)); endmodule less typing but same amount of thinking
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This note was uploaded on 05/10/2011 for the course ECE 18240 taught by Professor Hoe during the Fall '08 term at Carnegie Mellon.

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L06-CombSynVlog - Fall 2009 ECE 18-240 Fundamentals of...

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