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L10-FSM2Synthesis

# L10-FSM2Synthesis - Fall 2009 ECE 18-240 Fundamentals of...

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Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 10: FSM Implementation & Synthesis Don Thomas & William Nace Electrical & Computer Engineering Carnegie Mellon University LEC 10 10/2 Recitation 7 10/6 L10 FSM Design Chapter 7.1~7.8 Lab 2B 10/8 L11 FSM Design Chapter 7.1~7.8 10/9 Recitation: HW3 and Quiz 8 10/13 L12 Synchronous Digital Discipline Chapter 7.13, 8.1 Lab HW4 10/15 L13 RT-level Design Chapter 8 2B 10/16 Mid-Semester Break; No Recitations 9 10/20 L14 RT-level Design Chapter 8 Lab 3A 10/22 L15 RT-level Design Chapter 8 10/23 Recitation: HW4 and Quiz 10 10/27 L16 Feedback Circuits Chapter 7.2, 7.9 Lab 3B HW5 10/29 L17 Memory Technologies Chapter 9 10/30 Recitation: Lab Quiz 11 11/3 L19 Processor and ISA concept Lab 3C 11/5 L20 Assembly Language Fall-09 18-240 LEC5 — 18-240: Where are we. ..? ! 1 Handout: Lec10 " HW3 is out on BB -- number systems, and FSM topics " Lab 2B this week 2

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Fall-09 18-240 L10 — FSM Implementation & Synthesis ! What you know " State Transition Diagram and State Table " D Flip Flop ! What you don’t know " Traditional FSM design steps ! Today " The steps to FSM design plus a little Verilog 3 Fall-09 18-240 L10 — Terminology Review ! The clock is a special input in “synchronous” sequential logic " synchronizes the signal transitions of FFs and registers " allows combinational signals to settle before they “matter” again ! Two types of changes in logic signals " — The change is synchronized to an event ! The event is typically a repetitive one — like the clock in D-FF ! In normal operation, the output Q is synchronized to the clock event ! In normal operation, Q only changes when the event occurs, not when the input D changes " — The change is not synchronized to an event ! The reset is sometime “chosen/designed” to be asynchronous ! Example: edge-triggered D flip flop " normal operation of the data output are synchronized to the clock event " could have an asynchronous reset input to set output to zero immediately without waiting for the clock event. (We will see this today) 4
Fall-09 18-240 L10 — FSM — Review ! In the abstract, an Moore FSM can be defined by: " A set of states that the machine can be in " The inputs that steer the sequence of state transitions " The outputs as a combinational function of the current state (and inputs if Mealy). ! There are also two special inputs " A reset causes the FSM to transition to a special initial state " clock event sometimes called the sequencing event, that steps the FSM from one state to the next inputs outputs clock reset FSM 5 Fall-09 18-240 L10 — Moore and Mealy ! Moore machines ! Mealy machines inputs clock next state comb logic output comb. logic outputs output comb. logic inputs outputs clock next state comb logic Current State Register Current State Register 6

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Fall-09 18-240 L10 — FSMs: Traditional Synthesis ! Design Steps: " From word description, derive state diagram " Choose state assignment/encoding " Generate transition table " Generate excitation tables " From excitation tables, produce Boolean equations for F/F inputs (Next State Logic) and FSM outputs (Output Logic) " Implement using F/Fs and combinational logic
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L10-FSM2Synthesis - Fall 2009 ECE 18-240 Fundamentals of...

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