L11-FSM3StateAsg

# L11-FSM3StateAsg - Fall 2009 ECE 18-240 Fundamentals of...

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Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 11: FSM State Assignment Don Thomas & William Nace Electrical & Computer Engineering Carnegie Mellon University LEC 11 10/2 Recitation 7 10/6 L10 FSM Design Chapter 7.1~7.8 Lab 2B 10/8 L11 FSM Design Chapter 7.1~7.8 10/9 Recitation: HW3 and Quiz 8 10/13 L12 Synchronous Digital Discipline Chapter 7.13, 8.1 Lab HW4 10/15 L13 RT-level Design Chapter 8 2B 10/16 Mid-Semester Break; No Recitations 9 10/20 L14 RT-level Design Chapter 8 Lab 3A 10/22 L15 RT-level Design Chapter 8 10/23 Recitation: HW4 and Quiz 10 10/27 L16 Feedback Circuits Chapter 7.2, 7.9 Lab 3B HW5 10/29 L17 Memory Technologies Chapter 9 10/30 Recitation: Lab Quiz 11 11/3 L19 Processor and ISA concept Lab 3C 11/5 L20 Assembly Language Fall-09 18-240 LEC11 — 18-240: Where are we. ..? ! 1 Handout: Lec11 " HW3 is out on Bb; due this Fri in recitation " Lab2B, this week and next. 2

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Fall-09 18-240 LEC11 — FSMs: State Assignment ! What you know so far… " State Transition Diagrams/Tables " FSM formal design steps " Mealy vs Moore, and some timing issues " Verilog descriptions of FSMs ! What you don’t know: " Encoding, and State Assignment — Alternative design styles for selecting binary codes for FSM states " There are no good algorithms to do this by hand 3 Fall-09 18-240 LEC11 — Design Process Revisited Actually, there’s a little more choice here during design: - Encoding style - Then, do state assignment 1. State table, diagram 2. State assignment 3. Transition table 4. Excitation tables 5. Boolean eqns for Next State Logic, Output Logic X Q2 Q1 Q2’ D1 Q1 D2 Q2 Z clock reset reset reset Next State Logic Output Logic Q D Q D 4
Fall-09 18-240 LEC11 — State Transition Diagram: Revisited ! A little more on notation ! Whatever notation/convention you adopt, be consistent and make sure it is clearly defined Reset zero A one AB two ABC three BC G G G’ G’ Notation: outputs B and C are asserted Don’t care — G or G’ Specification • Four States: zero, one, two, three • Three Outputs: A, B, C • One Input: G 5 Fall-09 18-240 LEC11 — Encoding Styles 1: Fully Encoded ! Fully Encoded " ! log 2 #states " bits to encode " Assign a different code to each state ! Features " Minimizes number of FFs " Obvious binary encoding ! Drawbacks " May be hard to design and debug " May not minimize combinational logic State Assignment S 0 S 1 zero 0 0 two 0 1 one 0 1 three 1 1 Reset zero A one AB two ABC three BC G G G’ G’ 6

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Fall-09 18-240 LEC11 — Fully Encoded Implementation #FF= 2 #2-INPUT GATES= 6 #3-INPUT GATES= 1 S 1 S 0 A C B + S 1 S 0 + CLK G G S 1 S 0 S 0 S 1 S 1 S 0 resetN Q D Q D 7 Fall-09 18-240 LEC11 — Optimizations for Fully Encoded ! We just did an obvious assignment " Can we do better? i.e. Can we reduce the next state and/or output logic with different state assignments? ! Choices " With 4 states and 2 FFs, there are 4 choices for the first state, 3 for the second, 2 for the third, 1 for the last " 24 (which is 4!) different encodings. Which is best?
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## This note was uploaded on 05/10/2011 for the course ECE 18240 taught by Professor Hoe during the Fall '08 term at Carnegie Mellon.

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L11-FSM3StateAsg - Fall 2009 ECE 18-240 Fundamentals of...

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