L12-NEWA-TimingRules - Fall 2009 ECE 18-240 Fundamentals of...

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Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 12: FSM State Assignment Don Thomas & William Nace Electrical & Computer Engineering Carnegie Mellon University 9/11 Recitation: HW1 and Quiz 10/2 Recitation 7 10/6 L10 FSM Design Chapter 7.1~7.8 Lab 2B 10/8 L11 FSM Design Chapter 7.1~7.8 10/9 Recitation: HW3 and Quiz 8 10/13 L12 Synchronous Digital Discipline Chapter 7.13, 8.1 Lab 2B HW4 10/15 L13 RT-level Design Chapter 8 10/16 Mid-Semester Break; No Recitations 9 10/20 L14 RT-level Design Chapter 8 Lab 3A 10/22 L15 RT-level Design Chapter 8 10/23 Recitation: HW4 and Quiz 10 10/27 L16 Feedback Circuits Chapter 7.2, 7.9 Lab 3B HW5 10/29 L17 Memory Technologies Chapter 9 10/30 Recitation: Lab Quiz 11 11/3 L19 Processor and ISA concept Lab 3C 11/5 L20 Assembly Language Fall-09 18-240 LEC12 — 18-240: Where are we...? ! 1 Handout: Lec12 ! HW4 is out on Bb; due next Fri in recitation ! Lab2B, finishes this week (all sections) ! No recitation this week 2
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Fall-09 18-240 LEC12 — FSMs: Rules for Synchronous Design ! What you know so far… Gates, some FFs, state transition diagrams, Mealy/Moore State assignment and encoding ! What you don’t know Timing problems in FSM design Rules for synchronous FSM design ! The problem A design that is logically correct can still not work because of real-world implementation issues ! Need a set of rules for design When followed, “guarantees” proper operation of system “When ignored, may lead to timing problems” says Murphy 3 Fall-09 18-240 LEC12 — Timing Methodology: What is it? ! Set of rules? You mean I can’t just put gates and connections where I want? ! No! “Aw shucks, but why do we have these rules?” W e are working within a “synchronous digital abstraction”. To be correct, a design has to be correct with respect to the simplifying assumptions of the abstraction. You need to guarantee that a large complex circuit will work under a wide range of timing characteristics These rules reduce the complexity of design — an important issue when it comes to a team of several hundred people designing circuits with millions to billions of transistors. In short, it ain’t working until you see it with your own two eyes 4
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Fall-09 18-240 LEC12 — Synchronous Digital Abstraction ! All synchronous digital systems look something like this A clock to synchronize all FF state changes Combinational paths from FF outputs to FF inputs Combinational paths from external inputs to FF inputs Combinational paths from FF outputs to ext. outputs Combinational paths from external inputs to outputs 5 output comb. logic inputs outputs clock next state comb logic Current State Register Assumptions: Nice and Simple ! The CLOCK signal it is special, it is just there, and it is perfect the positive edges come at precisely the same interval ( T cyc , the cycle time or the clock period) all FFs (where ever they might be) see the same clock edge at precisely the same moment (aka synchronized ) !
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