L13-FSM4RTdatapath

L13-FSM4RTdatapath - Fall 2009 ECE 18-240 Fundamentals of...

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Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 13: Register-Transfer Datapath #1 Don Thomas & William Nace Electrical & Computer Engineering Carnegie Mellon University 8 10/13 L12 Synchronous Digital Discipline Chapter 7.13, 8.1 Lab HW4 10/15 L13 RT-level Design Chapter 8 2B 10/16 Mid-Semester Break; No Recitations 9 10/20 L14 RT-level Design Chapter 8 Lab 3A 10/22 L15 RT-level Design Chapter 8 10/23 Recitation: HW4 and Quiz 10 10/27 L16 Feedback Circuits Chapter 7.2, 7.9 Lab 3B HW5 10/29 L17 Memory Technologies Chapter 9 10/30 Recitation: Lab Quiz 11 11/3 L19 Processor and ISA concept Lab 3C 11/5 L20 Assembly Language 11/6 Recitation: HW5 and Quiz 12 11/10 Midterm 2 No Lab No HW 11/12 L21 Assembly Programming 11/13 Recitation: Lab Quiz Fall-09 18-240 LEC13 18-240: Where are we. ..? ! HW4 is out: State Assignment, R-T Logic, Verilog ! 2nd week of 2nd part of the 2nd Lab ! No recitation 2
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Fall-09 18-240 LEC13 Register-Transfer Datapath #1 ! What you know so far ! Combinational logic ! FSMs, aka Control ! Basic Timing ! What you don’t know ! How to build computational systems , aka Datapath ! Today — ! Let’s design an FSM to control something “useful”! ! No more of these sequence detectors ! Intro to register-transfer (RT) level systems 3 Fall-09 18-240 LEC13 Sequential Systems ! Every synchronous sequential design can be classified as a “finite-state” machine ! all that really means is that it has a finite number of flip- flop/registers in the design ! Intel Itanium2 has more than 2 27 state bits and more than 2 (2^27) distinguishable states ! No. There is not a gigantic state-transition diagram somewhere ! Yes. There are control FSMs (the way you understand FSMs now) ! may be many tens of states in the largest ones ! more complicated control exists as many cooperating FSMs ! The majority of the “logic” is in the datapath ! very stylistic usage of state and logic ! a very different way of design 4
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Fall-09 18-240 LEC13 Motivation: serial adder example ! Add two N-bit numbers in serial ! unsigned number appear 1 bit per cycle (LSB first) starting after reset ! assert “done”, “overflow” and “sum” when the computation is finished How many different states does this FSM need? 5 Reset Clk done overflow sum N ...Bi ...Ai Fall-09 18-240 LEC13 If you don’t know any better init reset " 0 + 0 " " 1 + 0 " " 1 + 1 " " 0 + 1 " 0,0 0,1 1,0 1,1 "0 0 + 0 0 " "0 0 + 0 1 " "0 1 + 0 0 " "0 1 + 0 1 " 0,0 0,1 1,0 1,1 "0 0 + 1 1 " "0 1 + 1 0 " "0 1 + 1 1 " "0 0 + 1 0 " 0,0 0,1 1,0 1,1 "00 0 + 10 0 " "00 0 + 10 1 " “00 1 + 10 0 " “00 1 + 10 1 " 0,0 0,1 1,0 1,1 This could work, but obviously not recommended. 6
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Fall-09 18-240 LEC13 A better idea: datapath + control ! Where is the “control” FSM? ! you need a separate FSM (not shown) that “counts” from 0 to N-1 after reset ! when FSM count is 0, all sum/carry flip flops get cleared; when FSM is N-1, you need to signal “done” ! only N states and log 2 N state bits!! ! Notice, the whole sequential system does have 2 (2^N) states, but they are in the datapath FA ……. .b i ……. .a i s co ci sum 7 Fall-09 18-240 LEC13 Datapath Design Abstractions 8
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Fall-09 18-240 LEC13 ld_L cl_L action 0 0 -- 0 1 load D 1 0 clear 1 1 hold RT Components: D-FF with features ! Certain features are so common they are a part of the FF library, e.g.
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This note was uploaded on 05/10/2011 for the course ECE 18240 taught by Professor Hoe during the Fall '08 term at Carnegie Mellon.

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L13-FSM4RTdatapath - Fall 2009 ECE 18-240 Fundamentals of...

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