L14-Datapath2 - Fall2009 ECE 18-240 Fundamentals of...

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1 Fall-09 18-240 L14 — Fall2009 ECE 18-240 Fundamentals of Computer Engineering LEC 14: Register-Transfer Datapath II Don Thomas & William Nace Electrical & Computer Engineering Carnegie Mellon University LEC 14 Fall-09 18-240 L14 — Week Date Lecture Reading Lab HW 10/8 L11 FSM Design Chapter 7.1~7.8 2B 10/9 Recitation: HW3 and Quiz Lab 8 10/13 L12 Synchronous Digital Discipline Chapter 7.13, 8.1 2B HW4 10/15 L13 RT-level Design Chapter 8 10/16 Mid-Semester Break; No Recitations 9 10/20 L14 RT-level Design Chapter 8 Lab 3A 10/22 L15 RT-level Design Chapter 8 10/23 Recitation: HW4 and Quiz 10 10/27 L16 Feedback Circuits Chapter 7.2, 7.9 Lab 3B HW5 10/29 L17 Memory Technologies Chapter 9 10/30 Recitation: Lab Quiz 11 11/3 L19 Processor and ISA concept Lab 3C 11/5 L20 Assembly Language 11/6 Recitation: HW5 and Quiz 12 11/10 Midterm 2 No Lab No HW 11/12 L21 Assembly Programming 11/13 Recitation: Lab Quiz 13 11/17 L22 Assembly Programming 2 Lab 4A HW6 11/19 L23 Microprocessor Design 1 11/20 Recitation 14 11/24 L24 Microprocessor Design 2 No Lab 11/26 Thanksgiving Break; no class 11/27 No recitations 18-240: Where are we. ..? 1 Handout: Lec14 HW4 – due this Friday in recitation Lab3 – Starting this week 2
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2 Fall-09 18-240 L14 — 3 Register-Transfer Datapath #2 What you know so far Combinational logic FSMs: design and optimization Basics of register transfer (RT) design What you don’t know How to build computational systems i.e. these might be general computers or application speci±c Today — Other register transfer design examples Plenty of alternate implementations Designing the optimum is not the issue here. Being able to understand and design an implementation is. Lec 14 Fall-09 18-240 L14 — 4 Review continued FSM-D — A ±nite state machine with a datapath A datapath is combinational logic and registers that can do computation Our goal? Basic design of these systems. Trade-o f s/optimizations left for other courses. clock reset inputs outputs FSM Datapath
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3 Fall-09 18-240 L14 — 5 Example — A Ones Counter Problem statement When the d_in_ready signal is asserted, read the 30-bit input word (d_in), count the number of bits in it that are set to one, make this 5-bit number available at the d_out output, assert the d_out_ready signal, and wait for the next d_in_ready signal So, we’ll build something like this How do the ports connect to the two internal parts? Fall-09 18-240 L14 — 6 Example: Serial Approach What we need: We need to hold the value we’re examining We could shift this value one place each time we examine a bit We need to count the number of bits to examine We need to count the number of ones
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4 Fall-09 18-240 L14 — 7 Shift Register module shiftR #(parameter w = 1) (input c, ld _L, sh _L, input [w-1:0] D, output lowBit); reg [w-1:0] Q; assign lowBit = Q[0]; always @(posedge c) begin if (~ld _L) Q <= D; else if (~sh _L) begin Q <= Q >> 1; Q[w-1] <= 0; end end endmodule lowbit D A load Q 0 lowbit A shift right Q Fall-09 18-240 L14 — 8
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This note was uploaded on 05/10/2011 for the course ECE 18240 taught by Professor Hoe during the Fall '08 term at Carnegie Mellon.

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L14-Datapath2 - Fall2009 ECE 18-240 Fundamentals of...

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