L15-FSM6LatchesFFs

L15-FSM6LatchesFFs - Fall 2009 ECE 18-240 Fundamentals of...

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Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 15: Latches/FFs: What’s Under the Hood Don Thomas & William Nace Electrical & Computer Engineering Carnegie Mellon University 1 Week Date Lecture Reading Lab HW 10/8 L11 FSM Design Chapter 7.1~7.8 2B 10/9 Recitation: HW3 and Quiz Lab 8 10/13 L12 Synchronous Digital Discipline Chapter 7.13, 8.1 2B HW4 10/15 L13 RT-level Design Chapter 8 10/16 Mid-Semester Break; No Recitations 9 10/20 L14 RT-level Design Chapter 8 Lab 3A 10/22 L15 RT-level Design Chapter 8 10/23 Recitation: HW4 and Quiz 10 10/27 L16 Feedback Circuits Chapter 7.2, 7.9 Lab 3B HW5 10/29 L17 Memory Technologies Chapter 9 10/30 Recitation: Lab Quiz 11 11/3 L19 Processor and ISA concept Lab 3C 11/5 L20 Assembly Language 11/6 Recitation: HW5 and Quiz 12 11/10 Midterm 2 No Lab No HW 11/12 L21 Assembly Programming 11/13 Recitation: Lab Quiz 13 11/17 L22 Assembly Programming 2 Lab 4A HW6 11/19 L23 Microprocessor Design 1 11/20 Recitation 14 11/24 L24 Microprocessor Design 2 No Lab 11/26 Thanksgiving Break; no class 11/27 No recitations Fall-09 18-240 LEC15 — 18-240: Where are we. ..? ! 1 Handout: Lec15 " HW4 due in Recitation this Friday; Lab 3B starts next week " HW Quiz = this Friday recitation; LAB Quiz = next Fri recit 2
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Fall-09 18-240 LEC15 — Latches/FFs: What’s Under the Hood ! What you know so far… " State transition diagrams " Steps in FSM design " Basic sequential elements (FFs) and their role in FSMs ! What you don’t know " How these sequential elements work " A lot of ugly timing problems ! Outline " Adding feedback to combinational circuits " Latches and flip flops " Timing and triggering issues always @(posedge ck) Q <= D; 3 Fall-09 18-240 LEC15 — Flip Flop Timing ! Previously… " We’ve presented FFs as black boxes, having certain port behaviors (i.e., we didn’t look inside) " Today — we’ll look into some of their timing requirements D Clock setup hold D held constant typically on order of a gate delay 4
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Fall-09 18-240 LEC15 — The Meta-Stable State ! What if setup or hold time not met? " You can get oscillations, or the flip flop may go into a meta- stable state ! The output may be read as 1 by parts of the circuit and 0 by others! " It could be there for an indefinite amount of time and you cannot predict which state it falls back into ! you may miss timing ! you may get the wrong answer " Ouch! ! Don’t violate timing (setup and hold) ! What about asynchronous inputs? D clock ? Q In time logic 0 logic 1 5 Fall-09 18-240 LEC15 — Simple Circuits with Memory/ Feedback ! Simplest example: 2 connected inverters " Primitive memory element created from cascaded gates " Simplest gate component: inverter " Basis for commercial Random Access Memory (static RAM) designs Cascaded Inverters: a bi-stable element Somehow, you need to be able to make Q a 1, or make it a 0. Tricky with this circuit. But once it is 1 or 0, it will hold the value.
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L15-FSM6LatchesFFs - Fall 2009 ECE 18-240 Fundamentals of...

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