L16-RTSystem3 - Fall 2009 ECE 18-240 Fundamentals of...

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Fall 2009 ECE 18-240 Fundamentals of Computer Engineering LEC 16: Testbenches and RTL Systems #3: Memories Carnegie Mellon University LEC 16 Week Date Lecture Reading Lab HW 10/8 L11 FSM Design Chapter 7.1~7.8 2B 10/9 Recitation: HW3 and Quiz Lab 8 10/13 L12 Synchronous Digital Discipline Chapter 7.13, 8.1 2B HW4 10/15 L13 RT-level Design Chapter 8 10/16 Mid-Semester Break; No Recitations 9 10/20 L14 RT-level Design Chapter 8 Lab 3A 10/22 L15 RT-level Design Chapter 8 10/23 Recitation: HW4 and Quiz 10 10/27 L16 Feedback Circuits Chapter 7.2, 7.9 Lab 3B HW5 10/29 L17 Memory Technologies Chapter 9 10/30 Recitation: Lab Quiz 11 11/3 L19 Processor and ISA concept Lab 3C 11/5 L20 Assembly Language 11/6 Recitation: HW5 and Quiz 12 11/10 Midterm 2 No Lab No HW 11/12 L21 Assembly Programming 11/13 Recitation: Lab Quiz 13 11/17 L22 Assembly Programming 2 Lab 4A HW6 11/19 L23 Microprocessor Design 1 11/20 Recitation 14 11/24 L24 Microprocessor Design 2 No Lab 11/26 Thanksgiving Break; no class 11/27 No recitations Fall-09 18-240 L16 — 18-240: Where are we. ..? ! 1 Handout: Lec16 " Lab 3B starting " Lab quiz in recit Friday (based on 3A) 2
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Fall-09 18-240 L16 — Testbench for synchronous designs ! What you know so far " Combinational logic and finite state machines " The basics of Register-transfer (RT) systems " Multibit components, Verilog parameter statement ! What you don’t know " How to write a testbench ! Today " One style — there are many " Most design groups/corporations have and enforce their own " This is all based on Homework 4, problem 4 ! There were some “quirks” put into the solution as food for discussion here 3 Fall-09 18-240 L16 — The Clock 4 module mpcTester #(parameter w = 1) (output reg clock, reset_L, input done, //from your output correct, //from your output output reg [w-1:0] data);//to your input reg[w-1:0] cksum;//used to calculate cksum of message sent always begin clock = 0; #5; forever #5 clock = ~clock; //all positive edges at multiples of 10 end 5 10 20 clock
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Fall-09 18-240 L16 — Asynchonous Reset 5 initial begin: testbench reset_L = 0; // reset the machine data = 8'h00; // set our outputs to zero #1 reset_L = 1; @(posedge clock); //statement will wait until time 10 // any statements put here will execute at time 10 @(posedge clock); data <= 8'h00; // statement executes at time 20 @(posedge clock); // time 30 1 reset_L always @(posedge clock, negedge reset_L) if (~reset_L) CS <= 0; else CS <= NS; This reset will trigger when reset_L changes from 1’bx (at simulator start up) to 1’b0 Fall-09 18-240 L16 — Asynchonous Reset 6 initial begin: testbench reset_L = 0; // reset the machine data = 8'h00; // set our outputs to zero #1 reset_L = 1; @(posedge clock); //statement will wait until time 10 // any statements put here will execute at time 10 // their left-hand sides will be updated at time 10, whether they // are blocking (=), or non-blocking (<=)
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L16-RTSystem3 - Fall 2009 ECE 18-240 Fundamentals of...

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