L17-Memories - Fall 2009 ECE 18-240 Structure and Design of...

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Fall 2009 ECE 18-240 Structure and Design of Digital Systems LEC 17: Memory Technologies Bill Nace and Don Thomas Carnegie Mellon University LEC 17 F09 18-240 L17 — 18-240: Where are we. ..? ! 1 Handout: Lec17 " HW5 is out on Blackboard " Lab3B this week; Lab Quiz this Fri in recitation 2 Exam2 approaches: All about seq stuff, from flip flops to FSMs to RTL (+ combinational arithmetic, L8)
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F09 18-240 L17 — Thanks for the Memories ! What you know so far " The basics of Register-transfer (RT) systems " Basics of using a memory device ! What you don’t know " Memory organization and control " SRAM and DRAM organizations Lec 17 3 F09 18-240 L17 — Hierarchy of Storage ! Basics " Bits ! Single bit flip flops " Registers ! A “word” of flip flops — e.g., an 8-bit register has 8 FFs, immediately accessible " Memories ! An array of registers — e.g., 1024 8-bit registers, one accessible at a time ! Actual implementations vary! " Disks ! Rotating magnetic/optic storage, accessible in blocks ! Longer wait, but more data per request " Archival / Cloud / etc ! Storage size and access time " Memory bits can be made very small if we don’t need immediate access " Memories and disks trade off density for speed " Memory density has grown faster than Moore’s law for electronics 4
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F09 18-240 L17 — Back to Basics — Storing a Value V c = q/C 5 R S Q Q' 0 1 Q ! Nor and Nand latches " The elemental building blocks of flip flops ! Back-to-back inverters " Used to build static RAM (SRAM) " Static — holds its value as long as power is applied ! Capacitors " Stores charge " Dynamic — charge leaks away Select Data (inout) F09 18-240 L17 — Accessing the Memory bit ! Use a pass transistor " If gate is logic one, drain and source are electrically connected " Otherwise there is a high resistance between them (disconnected) ! Add back-to-back inverters for storage " When not selected (gate equals logic zero), latch holds its value ! When selected, either: 6 Gate Drain Source Read: Lower inverter drives the data line Write: the data line overpowers the lower inverter (it typically has less driving power to allow this) Select Data (inout) Select Data (inout)
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Toward a Bigger Memory ! Arrange many bits of memory in words of length n " Selecting a word (a row) enables all bits in it to be accessed 7 Data bit 0 Data bit 1 Data bit n-1 Select word 0 Select word 1 Word 0 Word 1 F09 18-240 L17 — m to 2 m decoder A 0 A 1 A m-1 Address lines sel 0 sel 1 sel 2 sel 2 m -1 More Pieces: Remember Decoders? ! Decode m bits into 2 m lines " only one of which is asserted at any particular time ! Here the m-bit number A indicates the address of the memory word ! 8
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L17-Memories - Fall 2009 ECE 18-240 Structure and Design of...

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