L18-Proc&ISA

L18-Proc&ISA - Fall 2009 ECE 18-240 Structure and...

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Unformatted text preview: Fall 2009 ECE 18-240 Structure and Design of Digital Systems LEC 18: Computer System Abstractions, Instruction Set Architecture (ISA) Bill Nace & Don Thomas Electrical & Computer Engineering Carnegie Mellon University LEC 18 SPR09 18-240 LEC18 18-240: Where are we...? ! 2 Handouts: Lec18, P18240 Processor ASM " HW5 is due Friday " Recitation: HW Quiz 2 Midterm2 is still approaching! F09 18-240 L18 Midterm 2: Logistics ! Midterm 2 in-class on Tuesday, 10 November " 11/10 or 10/11, depending on your localization ! Closed book ! Two 2-sided 8.5-by-11 crib sheets " One old : midterm 1 crib sheet " One new : for materials since midterm 1 ! Covers materials presented up to last lec, including " Lecture 0~17 (but obviously, emphasis on Sequential stuff) ! Also emphasis on L8: Arithmetic " Assigned readings " Serialized handouts, HWs, labs, quizzes ! Expect similar difficulty and time-pressure as Midterm 1 3 F09 18-240 L18 Topics since Midterm 1 ! Finite state machine design " state transition diagrams, state assignment, gate-level implementations ! RTL-level sequential system design " datapath " sequence/control ! sequential elements " flip-flops and latches (use and design) " memory (use and design) ! Timing rules " setup, hold, skew.... ! Know your Verilog 4 F09 18-240 L18 Computer System Abstractions Applications Compilers OS Architecture (ISA) Microarchitecture Digital Design Circuits Devices/Physics To use an abstraction properly you must understand the limits of the abstraction 18-240 Part III digital logic transistors, signals atoms, electrons registers, ALU datapath hw/sw interface resource virtualization prog. languages human interface 5 F09 18-240 L18 Microprocessor Architecture, pt1 ! Big Question " How does a software program become physical hardware? ! What you know so far " High-End: Programming Languages ! Java, C, etc. " Low-End: Combinational, Sequential Design ! Gates, Flip-flops, FPGAs, etc. " Middle End: ! Register-transfer level design ! What you dont know " How to put it all together how to build a RT level design that will execute a program. ! This material not covered in textbook " Lecture Notes Lec 18 6 FSM-D HW Computation Model ! Hardware Thread FSM plus datapath " A datapath is combinational logic and registers that can do computation " The FSM controls the computation " So far, all examples have had a fixed function theyve been application specific ! Our next goal? " Build an FSM-D that can implement many different (universal) functions " How do we know what functions to include in this all encompassing FSM-D? " Seems like these functionalities should be specified after the fact some how....
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L18-Proc&ISA - Fall 2009 ECE 18-240 Structure and...

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