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L22-uP1 - Fall 2009 ECE 18-240 Structure and Design of...

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Fall 2009 ECE 18-240 Structure and Design of Digital Systems LEC 22: Microprocessor Design, Pt1 Bill Nace & Don Thomas Electrical & Computer Engineering Carnegie Mellon University LEC 22 F09 18-240 LEC22 — 18-240: Where are we...? ! 1 Handout: Lec22 " Lab 4 and HW6 starting up " Recitation: No quizzes 2
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F09 18-240 LEC22 — Micro-Processor Design, part 1 ! What you know so far… " For the P18240: All about assembly programming " Think of this as the MACROSCOPIC view of machine architecture ! What you don’t know " The MICROSCOPIC view — microarchitecture " What does the actual hardware look like ! stuff programmer cannot see " In effect, the RT level design ! Just notes, no readings Lec 22 3 F09 18-240 LEC22 — P18240 Architecture We have been talking about this picture as if it were reality, but it is nothing more than a convenient abstraction Over the next 3 lectures, we will reify it ! make the abstract into the concrete 4 R0 R1 R2 R3 R4 R5 R6 R7 PC SP general purpose registers special purpose registers ALU Z N C V condition codes Data [15:0] Address[15:0] (16 bit words) b15 ... b0 0000 0001 0002 0003 0004 FFFC FFFD FFFE FFFF Memory P18240 Processor
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F09 18-240 LEC22 — Central Processing Unit: Contents ! Control Path " Sends control signals to coordinate data path RTL " Responds to status signals from datapath " FSM ! Data Path " Combinational RTL " Functional units (ALU) do computation " Temporary storage in registers ! Including specialized registers (PC, SP) " 5 CPU Control Path Data Path Memory Instructions Control Signals Status Bits Data CPU FSM Data Path Memory Instructions Control Signals Data Addr Values MDR MAR ALU Register File Condition Codes Data Instr Addr F09 18-240 LEC22 — CPU Organization Interface to Memory Control Path Memory Data Register Memory Address Register Micro- Instruction (State Register) 6
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F09 18-240 LEC22 — Datapath Design ! What should you expect to find…? 1. Registers ! To store stuff, esp. addresses and data ! Such as: Register File, PC, SP, Instruction Register, etc 2. Functional Units ! To do computations ! Such as: Adders, ALUs, Multipliers, FPU 3. Interconnect ! Wires to connect things that need to communicate (i.e., busses) ! Such as: MUX, DEMUX, DECODER, TRI-STATE BUFFERS ! Allows logic to select which things are connected during any state of execution 7 010 F09 18-240 LEC22 — Generic Datapath Ex: For the ASM instruction R3 R2 + R1 000 001 011 100 101 + / - Register File ALU Logic Unit Destination Source A Source B ALU Operation (+/-, carry in) LU Operation (shift, no shift, shift in) A B (carry out, zero…) (shift out) Condition Codes μ -Instruction 110 111 011 010 001 Add No shift 8
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! Data Registers: R0 — R7 " How specified? " Instruction: ! rA — source and/or destination ! rB — source " Need to design a “register file” with ! 8 registers, ! 2 register specifiers (addresses), !
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