L23-uP2_handouts

L23-uP2_handouts - Fall 2009 ECE 18-240 Structure and...

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Unformatted text preview: Fall 2009 ECE 18-240 Structure and Design of Digital Systems LEC 23: Microprocessor Design Pt 2 Bill Nace & Don Thomas Electrical & Computer Engineering Carnegie Mellon University LEC 23 F09 18-240 L23 — 18-240: Where are we...? ! 1 Handout: Lec23 " No Lab, no Recitation, no Quiz, not much of anything this week " Except: Be thankful! 2 F09 18-240 L23 — Micro-Processor Design, part 2 ! What you know so far… " For the P18240: All about assembly programming " A datapath for the machine ! What you don’t know " The controller for the datapath " How to finish the RT level design " How to organize a Verilog description for such a design ! No reading, just notes. Lec 23 3 ! The CPU is organized as a hardware thread (FSM-D) with two components " Data Path ! Registers to store state ! Functional units modify state ! ALU ! Combinational ! Interconnect (Mux, Decoder) " Control Path ! FSM ! Puppeteer controlling data path ! Responds to status signals F09 18-240 L23 — Central Processing Unit 4 CPU Control Path Data Path Memory Instructions Control Signals Status Bits Data in[15:0] outA[15:0] outB[15:0] selB[2:0] selA[2:0] load inA inB opcode[3:0] F condCodes ALU 111 110 101 100 011 010 001 000 Dest[2:0] IR SP PC loadMDR loadMAR loadMDR RE RE MDR MAR WE To/From Memory Data loadMAR 00 01 10 11 00 01 10 11 loadCC ZCNV aluSrcA[1:0] aluSrcB[1:0] To Memory Address opCode Control Signals from FSM Status Signals to FSM Internal connections Datapath Entire Datapath Control Points FSM output ! Micro Instruction What the FSM can tell the Datapath to do! 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A A+1 A+B A+B+1 A-B-1 A-B A-1 B not(A) A • B A or B A ⊕ B shl(A) rol(A) lshr(A) ashr(A) F F 00 01 10 11 RegFile SP PC MDR op 000 001 010 011 100 101 110 111 RegFile SP PC MDR MAR IR (none) (none) dest 1 Load C.C. no-load 1 Read: MDR ! mem[MAR] no-read 1 Write: mem[MAR] ! MDR no write WE RE ldCC dest aluSrcB aluSrcA AluOpcode Specifies what the combinational logic does Specifies what registers and mems are loaded in this state F09 18-240 L23 — P18-240 FSM-D 7 Central Processing Unit (CPU) FSM opcode condCodes WE RE Lcc dest SrcB ScrA AluOp in[15:0] outA[15:0] outB[15:0] selB[2:0] selA[2:0] load inA inB opcode[3:0] F condCodes ALU 111 110 101 100 011 010 001 000 Dest[2:0] IR SP PC loadMDR loadMAR loadMDR RE RE MDR MAR WE To/From Memory Data loadMAR 00 01 10 11 00 01 10 11 loadCC ZCNV aluSrcA[1:0] aluSrcB[1:0] To Memory Address opCode Control Signals from FSM Status Signals to FSM Internal connections F09 18-240 L23 — NOW: Try some control examples ! Control points == micro-instruction " All the controls on FUs -- select ALU operation to perform " All the register and tri-state enables -- determine which regs loaded " All the mux selects -- determine which data gets sent where !...
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L23-uP2_handouts - Fall 2009 ECE 18-240 Structure and...

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