L24-uP3_handouts

L24-uP3_handouts - Fall 2009 ECE 18-240 Structure and...

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Fall 2009 ECE 18-240 Structure and Design of Digital Systems LEC 24: Microprocessor Design Pt 3 Carnegie Mellon University LEC 24 F09 18-240 L24 — 18-240: Where are we. ..? ! 1 Handout: Lec24 " Lab 4B: No Late Demos! " Recitation: HW6 and Quiz 2
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F09 18-240 L24 — Heads Up: Final ! Tue 15 Dec 8:30 AM-11:30 AM, UC McConomy " If you miss it, you retake the course next year ! Closed book ! “Three” 2-sided 8.5-by-11 crib sheets " two old: midterm 1 and 2 crib sheets " one new: for materials since midterm 2 " we provide: P18240 ISA Guide, a “Final Datapath Specification” and a “Some Mnemonics” sheet ! Covers materials including " Lecture 0~25 " Assigned readings " Serialized handouts, HWs, labs, quizzes ! Expect similar difficulty and time-pressure as Midterm 1 and 2, except 180 minutes 3 in[15:0] outA[15:0] outB[15:0] selB[2:0] selA[2:0] load inA inB opcode[3:0] F condCodes ALU 111 110 101 100 011 010 001 000 Dest[2:0] IR SP PC loadMDR loadMAR loadMDR RE RE MDR MAR WE To/From Memory Data loadMAR 00 01 10 11 loadCC ZCNV aluSrcA[1:0] aluSrcB[1:0] To Memory Address opCode Control Signals from FSM Status Signals to FSM Internal connections Final Datapath Specification
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Some mnemonics 00 01 10 11 RegFile SP PC MDR op `define MUX_REG 2'b00 `define MUX_SP 2'b01 `define MUX_PC 2'b10 `define MUX_MDR 2'b11 000 001 010 011 100 101 110 111 RegFile SP PC MDR MAR IR (none) (none) dest 0 1 Load C.C. no-load 0 1 Read: MDR ! mem[MAR] no-read 0 1 Write: mem[MAR] ! MDR no write 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A A+1 A+B A+B+1 A-B-1 A-B A-1 B not(A) A • B A + B A B shl(A) rol(A) lshr(A) ashr(A) F F `define F_A 4'b0000 `define F_A_PLUS_1 4'b0001 `define F_A_PLUS_B 4'b0010 `define F_A_PLUS_B_1 4'b0011 `define F_A_MINUS_B_1 4'b0100 `define F_A_MINUS_B 4'b0101 `define F_A_MINUS_1 4'b0110 `define F_B 4'b0111 `define F_A_NOT 4'b1000 `define F_A_AND_B 4'b1001 `define F_A_OR_B 4'b1010 `define F_A_XOR_B 4'b1011 `define F_A_SHL 4'b1100 `define F_A_ROL 4'b1101 `define F_A_LSHR 4'b1110 `define F_A_ASHR 4'b1111 `define MEM_RD 1'b0 `define MEM_WR 1'b0 `define LOAD_CC 1'b0 `define NO_LOAD 1'b1 `define DEST_REG 3'b000 `define DEST_SP 3'b001 `define DEST_PC 3'b010 `define DEST_MDR 3'b011 `define DEST_MAR 3'b100 `define DEST_IR 3'b101 `define DEST_NONE 3'b111 F09 18-240 L24 — Micro-Processor Design, part 3 ! What you know so far… " For the P18240: All about assembly programming " A datapath for the machine and how to control it ! What you don’t know " Verilog description for the whole processor " We’re not “just programming” ! Reading: Just notes Lec 24 6
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Decode F09 18-240 L24 — Review: A Hardwired Control Path A more-inclusive view … Decode IR=ADD not(A) A ! A+1 IR=NEG IR=LDI MAR ! PC PC++ RE'=0 Reg ! MDR One for each different opcode Fetch Inst Major Phases Execute 7 Fetch A ! A+B F09 18-240 L24 — Review: Fetch States in Verilog case (currState)
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This note was uploaded on 05/10/2011 for the course ECE 18240 taught by Professor Hoe during the Fall '08 term at Carnegie Mellon.

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L24-uP3_handouts - Fall 2009 ECE 18-240 Structure and...

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