L25-FPGAs_handouts

L25-FPGAs_handouts - Fall 2009 ECE 18-240 Structure and...

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Fall 2009 ECE 18-240 Structure and Design of Digital Systems LEC 25: An In-depth Look Into FPGAs Bill Nace & Don Thomas Electrical & Computer Engineering Carnegie Mellon University LEC 25 F09 18-240 L25 — 18-240: Where are we. ..? ! 1 Handout: Lec25 " Final: McConomy! " Recitation: HW6 and Quiz 2
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F09 18-240 L25 — Today: Advanced FPGAs ! History of FPGAs ! Close look at Xilinx Spartan 3 ! “Modern” FPGAs ! Note: Xilinx examples are used, but other companies also provide exceptional FPGAs " Especially Altera, Inc " Lattice Semiconductor " Others. .. 3 Not so long ago ! Digital logic implemented with chips " SSI, MSI, LSI, . .. " Small package complexity meant designs with lots of chips " Designs limited by inter-chip routing ! 18-240 taught with protoboards, wire-wrap, soldering ! Big designs implemented as ASICs " Full custom design ! Designer controls every transistor, route, I/O ! Expensive: thus only used for high-volume/high-end designs ! CPUs, commodity devices, sometimes special purpose " Standard cell design ! Low level functionality via library of silicon functions ! Performed slower, cheaper than full-custom " Gate Array ! Wafer manufactured with sea of primitives (inverters, NAND) ! Designer customizes upper metal layers to connect primitives
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F09 18-240 L25 — Enter the FPGA ! Xilinx XC3020 (~1990) ! 1st truly usable FPGA family ! 2 FFs per I/O ! Logic block: 2 LUTs, 2 FFs ! I/O: 5V TTL ! SRAM based ! Design entry via schematics or primitive HDL like ABEL " HDLs created for smaller primitive devices like PALs 5 (Courtesy Xilinx, Inc.) F09 18-240 L25 — Economic Argument for FPGAs ! FPGAs: High package cost ($300+), low NRE costs ! ASICs: Low package cost, high NRE costs ($600K+) 6 Development Cost + Device Cost Increasing NRE charge 58% are late to market -- impacts total volumes shipped ASIC cycle longer than some market windows Over 50% need to be respun Total Units Additional ASIC costs: Decreasing FPGA unit cost pushing crossover point to the right ASIC Trend FPGA Trend (Courtesy Xilinx, Inc.) FPGA solution has a lower total cost ASIC solution has a lower total cost
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F09 18-240 L25 — Early FPGA trends ! More than 20x bigger per decade ! More than 5x faster ! More than 50x cheaper 7 1/91 1/92 1/93 1/94 1/95 1/96 1/97 1/98 1/99 Year Capacity Speed Price 1 10 100 (Courtesy Xilinx, Inc.) F09 18-240 L25 — XC3020 8 CLB ( 64 total ) I / O Block ( 64 total ) General Purpose Interconnect IOBs have direct access to adjacent CLBs Switch Matrix (Courtesy Xilinx, Inc.)
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CLB: Configurable Logic Block ! Includes a Look-up Table (LUT) and F/F " Signal routing within CLB done with multiplexers ! In picture below, S determines if output comes from F/F or from LUT " Contents of LUT and multiplexer-based routing are controlled by configuration bits (static memory, fuses, etc) !
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L25-FPGAs_handouts - Fall 2009 ECE 18-240 Structure and...

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