23 Parallel Part 1 - Parallel Algorithms Part 1 15-211...

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Parallel Algorithms, Part 1 15-211: Fundamental Data Structures and Algorithms Margaret Reid-Miller 13 April 2010
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2 Announcements HW 6 (Chess) has been released Theory due: Tuesday, April 27 in lecture Program due: Wednesday, April 29 at 11:59pm You may have a partner Late days = max of partners’ late days No class Thursday – Carnival!
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3 Announcements ACM @ CMU Programming Competition Open to all students Teams of 2 Saturday, April 24, 1:00 pm- 4:00 pm To enter, email [email protected] Prizes!! Amazon Gift Cards and other goodies
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4 Last time… Linear-time sorting Bucket sort, radix sort Median-finding and order statistics
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5 Today Parallel Algorithms Models & terminology Parallel sum Prefix sum Quicksort
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Parallelism occurs everywhere n-body simulation computational fluid dynamics (airfoils) finite elements – structural design computer graphics – rendering, texture mapping protein folding 6
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Masses of data Web searches / web catalogs Genome Financial Store purchases (Walmart) Simulations Animations CAT scans and MRIs Estimated devices generate one zettabyte (2 21 bytes) per year! 7
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8 In the beginning … Moore’s Law The number of transistors on a chip doubles about every 2 years. Result: Until recently uniprocessor speeds per unit cost doubled every 18 months.
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9 Processor Performance From Hennessy & Patterson, 2007 RISC Performance (vs. VAX-11/780) “power wall”
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10 Power wall Problem: Higher clock rates more heat to dissipate per chip. Solution: Use multiple, slower processors (“cores”) per chip: multicores are more power efficient. Moore's Law continues! CPU clock speeds do not.
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11 Moore’s Law revisited The number of cores per chip will likely double every 2(?) years. Currently: A few cores/processors help workloads of a mix of independent serial tasks. Near future: Need to be able to use these (possibly hundreds of) cores/processors to make individual tasks faster. Hence: Every programmer needs to know how to design parallel algorithms!
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Parallelism at many architectural levels Logic gates: computer instructions executed by millions of logic gates Pipelining: overlap multiple instructions to increase clock rate MMX/Vector instructions: eg, graphics chips do vector arithmetic in parallel Multithreading: use multiple functional units and hide latency on single core * Multicores, supercomputers, clusters 12
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13 Parallelism Computer: The ability to perform multiple operations simultaneously.
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