4-5-6-Memory - ow Power Design ow Power Design Low Power...

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Unformatted text preview: ow Power Design ow Power Design Low Power Design Low Power Design Special Topics in Hardware Systems (CSV 881) Special Topics in Hardware Systems (CSV 881) w P w M O t i i t i w P w M O t i i t i Low Power Memory Optimisations Low Power Memory Optimisations Instructor: Preeti Ranjan Panda Department of Computer Science and Engineering Indian Institute of Technology, Delhi Contents Contents Low power caches and other optimisations Memory customisation (C) P. R. Panda, I.I.T Delhi 2 November 2008 Memory Optimisations Memory Optimisations Most memory-oriented performance optimisations reduce the NUMBER of memory accesses this also indirectly reduces power hence are mostly valid power optimisations also However, other optimisations can apply particularly when memory architecture is flexible (C) P. R. Panda, I.I.T Delhi 3 November 2008 ache Architecture ache Architecture Cache Architecture Cache Architecture READ Operation addr tag index off Tag Data Valid, Match hit? data November 2008 (C) P. R. Panda, I.I.T Delhi 4 Augmenting Cache Architectures Augmenting Cache Architectures Basic idea: add a small buffer/cache tores recent data stores recent data fetch directly from this buffer, inhibiting L1 cache access if high hit rate at buffer, power reduction November 2008 (C) P. R. Panda, I.I.T Delhi 5 Filter Filter Cache Cache Filter cache insert another small cache before L1 2 lower hit ratio reduces power CPU Filter Cache L1 L2 November 2008 (C) P. R. Panda, I.I.T Delhi 6 lock lock uffer uffer Block Block Buffer Buffer lock buffering g dex ff addr Block buffering save last accessed cache line in buffer next access is to same ag ata tag index off if next access is to same line, read directly from buffer saves access to memory Tag Data y core when spatial locality exists extend to small fully Buf Buf Valid, Match hit? ata associative buffer data November 2008 (C) P. R. Panda, I.I.T Delhi 7 Scratch Pad Memory Scratch Pad Memory On-chip Memory 1 cycle P-1 ff- ip Data ache CPU Address pace P ompiler Managed Memory Off chip Memory Cache (on-chip) Space 1 cycle 10-20 cycles Compiler Managed Memory part of memory space directly addressed can be on-chip SRAM N-1 fast, predictable, low power vs. cache Embedded processors, IBM Cell What data / code should reside in Scratch Pad?...
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This note was uploaded on 05/10/2011 for the course CSCI 500 taught by Professor Assdullah during the Spring '11 term at Northern Virginia.

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4-5-6-Memory - ow Power Design ow Power Design Low Power...

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