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cs33-memory

cs33-memory - The The Memory Hierarchy Chapter 5 of B&O...

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The Memory Hierarchy Some notes adopted from Bryant and O’Hallaron Chapter 5 of B&O
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The CPU The CPU-Memory Gap Memory Gap http://blogs.sun.com/toddjobson/entry/processors_and_performance_chips_mips
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Random Random-Access Memory (RAM) Access Memory (RAM) • Key features – RAM is packaged as a chip. – Basic storage unit is a cell (one bit per cell). – Multiple RAM chips form a memory. • Static RAM ( SRAM ) – Each cell stores bit with a six-transistor circuit. – Retains value indefinitely, as long as it is kept powered. – Relatively insensitive to disturbances such as electrical noise. – Faster and more expensive than DRAM. • Dynamic RAM ( DRAM ) – Each cell stores bit with a capacitor and transistor. – Value must be refreshed every 10-100 ms. – Sensitive to disturbances. – Slower and cheaper than SRAM.
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Problem: Processor -Memory Bottleneck Memory Bottleneck Main Memory CPU Reg Processor performance doubled about every 18 months Bus bandwidth evolved much slower Core 2 Duo: Can process at least 256 Bytes/cycle (1 SSE two operand add and mult) Core 2 Duo: Bandwidth 2 Bytes/cycle Latency 100 cycles Solution: Caches
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Cache • Definition: Computer memory with short access time used for the storage of frequently or recently used instructions or data
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General Cache Mechanics 8 9 14 3 Cache Data is copied in block-sized Smaller, faster, more expensive memory caches a subset of the blocks 4 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Memory Larger, slower, cheaper memory viewed as partitioned into “blocks” transfer units 4 10
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General Cache Concepts: Hit 8 9 14 3 Cache Data in block b is needed Request: 14 Block b is in cache: Hit! 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Memory
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General Cache Concepts: Miss 8 9 14 3 Cache Data in block b is needed Request: 12 Block b is not in cache: Miss! Block b is fetched from Request: 12 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Memory memory 12 Block b is stored in cache Placement policy: determines where b goes Replacement policy: determines which block gets evicted (victim)
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Cache Performance Metrics • Miss Rate – Fraction of memory references not found in cache (misses/references) – Typical numbers: • 3-10% for L1 • can be quite small (e.g., < 1%) for L2, depending on size, etc. • Hit Time – Time to deliver a line in the cache to the processor (includes time to determine whether the line is in the cache) – Typical numbers: • 1-2 clock cycles for L1 • 5-20 clock cycles for L2 • Miss Penalty – Additional time required because of a miss • Typically 50-200 cycles for main memory (Trend: increasing!)
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Lets think about those numbers • Huge difference between a hit and a miss – Could be 100x, if just L1 and main memory • Would you believe 99% hits is twice as good as 97%? – Consider: cache hit time of 1 cycle miss penalty of 100 cycles – Average access time: 97% hits: 1 cycle + 0.03 * 100 cycles = 4 cycles 99% hits: 1 cycle + 0.01 * 100 cycles = 2 cycles • This is why “miss rate” is used instead of “hit rate”
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Why Caches Work • Principle of Locality:
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