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50
VLSI Test Principles and Architectures
where
i
=
0, 1,
±±±
,
n
−
1. On the other hand, the probabilitybased observability
of an input
l
at stage
i
on an output
s
k
—O(
l
,
s
k
), where
k>i
—depends on the
propagation of the carry output from stage
i
to the output
s
k
. This calculation is
left as a problem at the end of this chapter.
In general, RTL testability analysis can sometimes lead to more accurate results
than gatelevel testability analysis. The reason is that the number of reconvergent
fanouts in an RTL model is usually much less than that in a gatelevel model. RTL
testability analysis is also more time efficient than gatelevel testability analysis
because an RTL model is much simpler than an equivalent gatelevel model; how
ever, the practical application of RTL testability analysis for testability enhancement
in complex RTL designs remains a challenging research topic.
2.3
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 Spring '08
 elbarki

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