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In Praise of VLSI Test Principles and Architectures: Design for Testability Testing techniques for VLSI circuits are today facing many exciting and complex challenges. In the era of large systems embedded in a single system-on-chip (SOC) and fabricated in continuously shrinking technologies, it is important to ensure correct behavior of the whole system. Electronic design and test engineers of today have to deal with these complex and heterogeneous systems (digital, mixed-signal, memory), but few have the possibility to study the whole field in a detailed and deep way. This book provides an extremely broad knowledge of the discipline, covering the fundamentals in detail, as well as the most recent and advanced concepts. It is a textbook for teaching the basics of fault simulation, ATPG, memory testing, DFT and BIST. However, it is also a complete testability guide for an engineer who wants to learn the latest advances in DFT for soft error protection, logic built-in self-test (BIST) for at-speed testing, DRAM BIST, test compression, MEMS testing, FPGA testing, RF testing, etc.
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