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8_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

8_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 11...

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C ONTENTS Preface xxi In the Classroom xxiv Acknowledgments xxv Contributors xxvii About the Editors xxix 1 Introduction 1 Yinghua Min and Charles Stroud 1.1 Importance of Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Testing During the VLSI Lifecycle . . . . . . . . . . . . . . . . . . . . 2 1.2.1 VLSI Development Process . . . . . . . . . . . . . . . . . . . . 3 1.2.1.1 Design Verification . . . . . . . . . . . . . . . . . . 4 1.2.1.2 Yield and Reject Rate . . . . . . . . . . . . . . . . . 5 1.2.2 Electronic System Manufacturing Process . . . . . . . . . . . 6 1.2.3 System-Level Operation . . . . . . . . . . . . . . . . . . . . . 6 1.3 Challenges in VLSI Testing . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.1 Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2 Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Unformatted text preview: 11 1.3.2.1 Stuck-At Faults . . . . . . . . . . . . . . . . . . . . 12 1.3.2.2 Transistor Faults . . . . . . . . . . . . . . . . . . . 15 1.3.2.3 Open and Short Faults . . . . . . . . . . . . . . . . 16 1.3.2.4 Delay Faults and Crosstalk . . . . . . . . . . . . . . 19 1.3.2.5 Pattern Sensitivity and Coupling Faults . . . . . . 20 1.3.2.6 Analog Fault Models . . . . . . . . . . . . . . . . . 21 1.4 Levels of Abstraction in VLSI Testing . . . . . . . . . . . . . . . . . . 22 1.4.1 Register-Transfer Level and Behavioral Level . . . . . . . . . 22 1.4.2 Gate Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4.3 Switch Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.4.4 Physical Level . . . . . . . . . . . . . . . . . . . . . . . . . . . 24...
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