10_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

10_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Contents ix 2.6.3 Gated Clocks. ........................... 71 2.6.4 Derived Clocks. .......................... 74 2.6.5 Combinational Feedback Loops. ................ 74 2.6.6 Asynchronous Set/Reset Signals. ................ 75 2.7 Scan Design Flow. ............................. 76 2.7.1 Scan Design Rule Checking and Repair . ........... 77 2.7.2 Scan Synthesis. .......................... 78 2.7.2.1 Scan Configuration . ................. 79 2.7.2.2 Scan Replacement. .................. 82 2.7.2.3 Scan Reordering. ................... 82 2.7.2.4 Scan Stitching. .................... 83 2.7.3 Scan Extraction . ......................... 83 2.7.4 Scan Verification . ........................ 84 2.7.4.1 Verifying the Scan Shift Operation. ........ 85
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