11_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

11_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - x...

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Unformatted text preview: x Contents 3.2.3.3 Input Counting . . . . . . . . . . . . . . . . . . . . . 116 3.2.3.4 Parallel Gate Evaluation . . . . . . . . . . . . . . . 116 3.2.4 Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.2.4.1 Transport Delay . . . . . . . . . . . . . . . . . . . . 118 3.2.4.2 Inertial Delay . . . . . . . . . . . . . . . . . . . . . . 119 3.2.4.3 Wire Delay . . . . . . . . . . . . . . . . . . . . . . . 119 3.2.4.4 Functional Element Delay Model . . . . . . . . . . 120 3.3 Logic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.3.1 Compiled-Code Simulation . . . . . . . . . . . . . . . . . . . 121 3.3.1.1 Logic Optimization . . . . . . . . . . . . . . . . . . 121 3.3.1.2 Logic Levelization . . . . . . . . . . . . . . . . . . . 123 3.3.1.3 Code Generation . . . . . . . . . . . . . . . . . . . . 124 3.3.2 Event-Driven Simulation . . . . . . . . . . . . . . . . . . . . . 125 3.3.2.1 Nominal-Delay Event-Driven Simulation . . . . . 126 3.3.3 Compiled-Code...
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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