12_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

12_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Contents xi 4.4 Designing a Stuck-At ATPG for Combinational Circuits. ....... 169 4.4.1 A Naive ATPG Algorithm. .................... 169 4.4.1.1 Backtracking. ..................... 172 4.4.2 A Basic ATPG Algorithm. .................... 173 4.4.3 D Algorithm . ........................... 177 4.4.4 PODEM. .............................. 182 4.4.5 FAN . ................................ 186 4.4.6 Static Logic Implications. .................... 187 4.4.7 Dynamic Logic Implications. .................. 191 4.5 Designing a Sequential ATPG. ...................... 194 4.5.1 Time Frame Expansion. ..................... 194 4.5.2 5-Valued Algebra Is Insufficient. ................ 196 4.5.3 Gated Clocks and Multiple Clocks . .............. 197
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