13_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

13_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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xii Contents 5 Logic Built-In Self-Test 263 Laung-Terng (L.-T.) Wang 5.1 Introduction . ................................ 264 5.2 BIST Design Rules . ............................ 266 5.2.1 Unknown Source Blocking. ................... 267 5.2.1.1 Analog Blocks . .................... 267 5.2.1.2 Memories and Non-Scan Storage Elements. ...268 5.2.1.3 Combinational Feedback Loops. .......... 268 5.2.1.4 Asynchronous Set/Reset Signals. .......... 268 5.2.1.5 Tristate Buses . .................... 269 5.2.1.6 False Paths. ...................... 270 5.2.1.7 Critical Paths. ..................... 270 5.2.1.8 Multiple-Cycle Paths . ................ 270 5.2.1.9 Floating Ports . .................... 270 5.2.1.10 Bidirectional I/O Ports . ............... 271 5.2.2 Re-Timing . ............................ 271
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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