14_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

14_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Contents xiii 5.5.3.2 Modified Built-In Logic Block Observer. ..... 300 5.5.3.3 Concurrent Built-In Logic Block Observer. ....300 5.5.3.4 Circular Self-Test Path (CSTP) . .......... 302 5.5.4 BIST Architectures Using Concurrent Checking Circuits . .............................. 303 5.5.4.1 Concurrent Self-Verification. ............ 303 5.5.5 Summary. ............................. 304 5.6 Fault Coverage Enhancement. ...................... 304 5.6.1 Test Point Insertion. ....................... 305 5.6.1.1 Test Point Placement. ................ 306 5.6.1.2 Control Point Activation . .............. 307 5.6.2 Mixed-Mode BIST. ........................ 308 5.6.2.1 ROM Compression . ................. 308 5.6.2.2 LFSR Reseeding. ................... 308 5.6.2.3 Embedding Deterministic Patterns. ........ 309
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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