16_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

16_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Contents xv 7 Logic Diagnosis 397 Shi-Yu Huang 7.1 Introduction . ................................ 397 7.2 Combinational Logic Diagnosis. ..................... 401 7.2.1 Cause–Effect Analysis. ...................... 401 7.2.1.1 Compaction and Compression of Fault Dictionary 403 7.2.2 Effect–Cause Analysis. ...................... 405 7.2.2.1 Structural Pruning . ................. 407 7.2.2.2 Backtrace Algorithm . ................ 408 7.2.2.3 Inject-and-Evaluate Paradigm. ........... 409 7.2.3 Chip-Level Strategy. ....................... 418 7.2.3.1 Direct Partitioning . ................. 418 7.2.3.2 Two-Phase Strategy. ................. 420 7.2.3.3 Overall Chip-Level Diagnostic Flow. ........ 424 7.2.4 Diagnostic Test Pattern Generation. .............. 425 7.2.5 Summary of Combinational Logic Diagnosis . ........ 426
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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