17_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

17_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Unformatted text preview: xvi Contents 8.2.5 Comparison of RAM Test Patterns . . . . . . . . . . . . . . . 471 8.2.6 Word-Oriented Memory . . . . . . . . . . . . . . . . . . . . . 473 8.2.7 Multi-Port Memory . . . . . . . . . . . . . . . . . . . . . . . . 473 8.3 RAM Fault Simulation and Test Algorithm Generation . . . . . . . . 475 8.3.1 Fault Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 476 8.3.2 RAMSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 8.3.3 Test Algorithm Generation by Simulation . . . . . . . . . . . 480 8.4 Memory Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . 488 8.4.1 RAM Specification and BIST Design Strategy . . . . . . . . . 489 8.4.2 BIST Architectures and Functions . . . . . . . . . . . . . . . 493 8.4.3 BIST Implementation . . . . . . . . . . . . . . . . . . . . . . . 495 8.4.4 BRAINS: A RAM BIST Compiler . . . . . . . . . . . . . . . . 500 8.5 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 8.6 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509Exercises ....
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