18_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

18_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Contents xvii 10 Boundary Scan and Core-Based Testing 557 Kuen-Jong Lee 10.1 Introduction. ............................... 558 10.1.1 IEEE 1149 Standard Family. ................. 558 10.1.2 Core-Based Design and Test Considerations. ........ 559 10.2 Digital Boundary Scan (IEEE Std. 1149.1) . ............. 561 10.2.1 Basic Concept . ......................... 561 10.2.2 Overall 1149.1 Test Architecture and Operations. ..... 562 10.2.3 Test Access Port and Bus Protocols. ............. 564 10.2.4 Data Registers and Boundary-Scan Cells . ......... 565 10.2.5 TAP Controller. ......................... 567 10.2.6 Instruction Register and Instruction Set. .......... 569 10.2.7 Boundary-Scan Description Language. ........... 574 10.2.8 On-Chip Test Support with Boundary Scan. ........ 574 10.2.9 Board and System-Level Boundary-Scan Control
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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