24_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

24_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Preface xxiii Chapter 6 then jumps into the most important test cost aspect of testability inser- tion into a scan design . How cost reduction can be achieved using test compression is discussed in greater detail. Representative, commercially available compression tools are introduced so readers (practitioners) can appreciate what is best suited to their needs. Chapter 7 delves into the topic of logic diagnosis. Techniques for combinational logic diagnosis based on cause–effect analysis , effect–cause analysis , and chip-level strategy are first described. Then, innovative techniques for scan chain diagnosis and logic BIST diagnosis are explained in detail. Chapter 8 and Chapter 9 cover the full spectrum of memory test and diagnosis methods. In both chapters, after a description of basic memory test and diagnosis concepts, memory BIST and memory BISR architectures are then explained in detail. Memory fault simulation
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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