36_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

36_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Introduction 5 This physical-level description is used to verify that the final design will meet timing and operating frequency specifications. There are many tools available to assist in the design verification process includ- ing computer-aided design (CAD) synthesis and simulation tools, hardware emu- lation, and formal verification methods; however, design verification takes time, and insufficient verification fails to detect design errors. As a result, design verifi- cation is economically significant as it has a definite impact on time-to-market. It is interesting to note that many design verification techniques are borrowed from test technology because verifying a design is similar to testing a physical product. Furthermore, the test stimuli developed for design verification of the RTL, logical, and physical levels of abstraction are often used, in conjunction with the associ- ated output responses obtained from simulation, to test the VLSI device during the manufacturing process. 1.2.1.2
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online