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36_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

36_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Introduction 5 This physical-level description is used to verify that the final design will meet timing and operating frequency specifications. There are many tools available to assist in the design verification process includ- ing computer-aided design (CAD) synthesis and simulation tools, hardware emu- lation, and formal verification methods; however, design verification takes time, and insufficient verification fails to detect design errors. As a result, design verifi- cation is economically significant as it has a definite impact on time-to-market. It is interesting to note that many design verification techniques are borrowed from test technology because verifying a design is similar to testing a physical product. Furthermore, the test stimuli developed for design verification of the RTL, logical, and physical levels of abstraction are often used, in conjunction with the associ- ated output responses obtained from simulation, to test the VLSI device during the manufacturing process.
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