40_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

40_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Introduction 9 ± FIGURE 1.6 IBM CMOS integrated circuit with six levels of interconnections and effective transistor channel length of 0 ± 12 ² m [Geppert 1998]. be more susceptible to failures of transistors and wires due to soft (cosmic) errors, process variations, electromigration, and material aging. As the integration scale increases, more transistors can be fabricated on a single chip, thus reducing the cost per transistor; however, the difficulty of testing each transistor increases due to the increased complexity of the VLSI device and increased potential for defects, as well as the difficulty of detecting the faults produced by those defects. This trend is further accentuated by the competitive price pressures of the high-volume
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: consumer market, as well as by the emergence of system-on-chip (SOC) imple-mentations; mixed-signal circuits and systems, including radiofrequency (RF); and microelectromechanical systems (MEMSs). 1.3.1 Test Generation A fault is a representation of a defect reflecting a physical condition that causes a circuit to fail to perform in a required manner. A failure is a deviation in the performance of a circuit or system from its specified behavior and represents an irreversible state of a component such that it must be repaired in order for it to provide its intended design function. A circuit error is a wrong output signal...
View Full Document

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online