42_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

42_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Introduction 11 usually a difficult task. Fault coverage is linked to the yield and the defect level by the following expression [Williams 1981]: Defect level = 1 yield ± 1 fault coverage ² From this equation, we can show that a PCB with 40 chips, each having 90% fault coverage and 90% yield, could result in a reject rate of 41.9%, or 419,000 PPM. As a result, improving fault coverage can be easier and less expensive than improving manufacturing yield because making yield enhancements can be costly; therefore, generating test stimuli with high fault coverage is very important. Any input pattern, or sequence of input patterns, that produces a different output response in a faulty circuit from that of the fault-free circuit is a test vector ,or sequence of test vectors, that will detect the faults. The goal of test generation is to find an efficient set of test vectors that detects all faults considered for that circuit. Because a given set of test vectors is usually capable of detecting many faults in a
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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