45_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

45_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 14...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
14 VLSI Test Principles and Architectures collapsing typically reduces the total number of faults by 50 to 60% [Bushnell 2000]. Fault collapsing for stuck-at faults is based on the fact that a SA0 at the input to an AND (NAND) gate is equivalent to the SA0 (SA1) at the output of the gate. Similarly, a SA1 at the input to an OR (NOR) gate is equivalent to the SA1 (SA0) at the output of the gate. For an inverter, a SA0 (SA1) at the input is equivalent to the SA1 (SA0) at the output of the inverter. Furthermore, a stuck-at fault at the source (output of the driving gate) of a fanout-free net is equivalent to the same stuck-at fault at the destination (gate input being driven). Therefore, the number of collapsed stuck-at faults in any combinational circuit constructed from elementary logic gates (AND, OR, NAND, NOR, and inverter) is given by: Number of collapsed faults = 2 × ±number of POs + number of fanout stems² + total number of gate ±including inverter² inputs total number of inverters
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online