47_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

47_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 16...

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16 VLSI Test Principles and Architectures The circuit in Figure 1.8 has a total of eight (2 × 4) possible single transistor faults; however, there are equivalent faults at the transistor level, as stuck-open faults in a group of series transistors (such as P 1 and P 2 ) are indistinguishable. The same holds true for stuck-short faults in a group of parallel transistors (such as N 1 and N 2 ); therefore, fault collapsing can be applied to transistor-level circuits [Stroud 2002]. The number of collapsed transistor faults in a circuit is given by: Number of collapsed faults = 2 × T T S + G S T P + G P where T is the total number of transistors, T S is the total number of transistors in series, G S is the total number of groups of transistors in series, T P is the total number of transistors in parallel, and G P is the total number of groups of transistors in parallel. For the two-input NOR gate of Figure 1.8, there are four transistors ( T = 4), two transistors ( P 1 and P 2 ) in the only group of series transistors (
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