48_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

48_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Introduction 17 stuck-open faults when the faulty wire segment is interconnecting transistors to form gates. On the other hand, opens tend to behave like stuck-at faults when the faulty wire segment is interconnecting gates. Therefore, a set of test vectors that provide high stuck-at fault coverage and high transistor fault coverage will also detect open faults; however, a resistive open does not behave the same as a transistor or stuck-at fault but instead affects the propagation delay of the signal path, as will be discussed in the next subsection. A short between two elements is commonly referred to as a bridging fault . These elements can be transistor terminals or connections between transistors and gates. The case of an element being shorted to power (V DD ) or ground (V SS ) is equivalent to the stuck-at fault model; however, when two signal wires are shorted together, bridging fault models are required. In the first bridging fault model proposed, the logic value of the shorted nets was modeled as a logical AND or OR of the logic
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: values on the shorted wires. This model is referred to as the wired-AND / wired-OR bridging fault model. The wired-AND bridging fault means the signal net formed by the two shorted lines will take on a logic 0 if either shorted line is sourcing a logic 0, while the wired-OR bridging fault means the signal net will take on a logic 1 if either of the two lines is sourcing a logic 1. Therefore, this type of bridging fault can be modeled with an additional AND or OR gate, as illustrated in Figure 1.9a, where A S and B S denote the sources for the two shorted signal nets and A D and B D source bridging fault destination A S B S A D B D Wired-AND A S B S A D B D Wired-OR (a) (b) (c) A S A D B S B D A dominant-AND B A S B S A dominant-OR B B dominant-AND A B dominant-OR A A D A S B D B S B D A D A S B S B D A D A S B S B D A D A dominates B B dominates A B D A D A S B S B D A D A S B S ± FIGURE 1.9 Bridging fault models....
View Full Document

This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

Ask a homework question - tutors are online