18VLSI Test Principles and ArchitecturesTABLE 1.3±Truth Tables for Bridging Fault Models of Figure 1.9ASBS00011011ADBDWired-AND00Wired-OR11A dominates B0011B dominates AA dominant-AND B00B dominant-AND AA dominant-OR B11B dominant-OR Adenote the destinations for the two nets. The truth tables for fault-free and faultybehavior are given in Table 1.3.The wired-AND/wired-OR bridging fault model was originally developed for bipo-lar VLSI and does not accurately reflect the behavior of bridging faults typicallyfound in CMOS devices; therefore, thedominant bridging faultmodel was pro-posed for CMOS VLSI where one driver is assumed to dominate the logic value onthe two shorted nets. Two fault types are normally evaluated per fault site, whereeach driver is allowed to dominate the logic value on the shorted signal net (seeFigure 1.9b). The dominant bridging fault model is more difficult to detect because
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