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18 VLSI Test Principles and Architectures TABLE 1.3 ± Truth Tables for Bridging Fault Models of Figure 1.9 A S B S 00 01 10 11 A D B D Wired-AND 0 0 Wired-OR 1 1 A dominates B 0 0 1 1 B dominates A A dominant-AND B 0 0 B dominant-AND A A dominant-OR B 1 1 B dominant-OR A denote the destinations for the two nets. The truth tables for fault-free and faulty behavior are given in Table 1.3. The wired-AND/wired-OR bridging fault model was originally developed for bipo- lar VLSI and does not accurately reflect the behavior of bridging faults typically found in CMOS devices; therefore, the dominant bridging fault model was pro- posed for CMOS VLSI where one driver is assumed to dominate the logic value on the two shorted nets. Two fault types are normally evaluated per fault site, where each driver is allowed to dominate the logic value on the shorted signal net (see Figure 1.9b). The dominant bridging fault model is more difficult to detect because
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