50_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

50_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Introduction 19 fault sites. While there are many signal nets in a VLSI circuit, it is impractical to evaluate detection of bridging faults between any possible pair of nets; for example, a circuit with N signal nets would have N - choose -2 = N × N 1 / 2 possible fault sites, but a bridging fault between two nets on opposite sides of the device may not be possible. One solution to this problem is to extract likely bridging fault sites from the physical design after physical layout. 1.3.2.4 Delay Faults and Crosstalk Fault-free operation of a logic circuit requires not only performing the logic function correctly but also propagating the correct logic signals along paths within a specified time limit. A delay fault causes excessive delay along a path such that the total propagation delay falls outside the specified limit. Delay faults have become more prevalent with decreasing feature sizes. There are different delay fault models. In the gate-delay fault and the transition fault
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