20 VLSI Test Principles and Architectures are used to test the path delay from input x 2 , through the inverter and lower AND gate, to the output y . Assuming the transition between the two test vectors occurs at time t = 0, the resulting transition propagates through the circuit with the fault-free delays shown at each node in the circuit such that we expect to see the transition at the output y at time t = 7. A delay fault along this path would create a transition at some later time, t> 7. Of course, this measurement could require a high-speed, high-precision test machine. With decreasing feature sizes and increasing signal speeds, the problem of mod-eling gate delays becomes more difficult. As technologies approach the deep sub-micron region, the portion of delay contributed by gates reduces while the delay due to interconnect becomes dominant. This is because the interconnect lengths do not scale in proportion to the shrinking area of transistors that make up the gates. In addition, if the operating frequencies also increase with scaling, then the
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