20VLSI Test Principles and Architecturesare used to test the path delay from inputx2, through the inverter and lower ANDgate, to the outputy. Assuming the transition between the two test vectors occurs attimet=0, the resulting transition propagates through the circuit with the fault-freedelays shown at each node in the circuit such that we expect to see the transitionat the outputyat timet=7. A delay fault along this path would create a transitionat some later time,t >7. Of course, this measurement could require a high-speed,high-precision test machine.With decreasing feature sizes and increasing signal speeds, the problem of mod-eling gate delays becomes more difficult. As technologies approach the deep sub-micron region, the portion of delay contributed by gates reduces while the delaydue to interconnect becomes dominant. This is because the interconnect lengthsdo not scale in proportion to the shrinking area of transistors that make up thegates. In addition, if the operating frequencies also increase with scaling, then the
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The Circuit, rams, Electronic design, 188.8.131.52, Crosstalk delay