53_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

53_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES - 22...

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22 VLSI Test Principles and Architectures 1.4 LEVELS OF ABSTRACTION IN VLSI TESTING In the design hierarchy, a higher level description has fewer implementation details but more explicit functional information than a lower level description. As described in Section 1.2.1.1, the various levels of abstraction include behavioral (architecture), register-transfer, logical (gate), and physical (transistor) levels. The hierarchical design process lends itself to hierarchical test development, but the fault models described in the previous section are more appropriate for particular levels of abstraction. In this section, we discuss test generation and the use of fault models at these various levels of abstraction. 1.4.1 Register-Transfer Level and Behavioral Level The demand for CAD tools for the design of digital circuits at high levels of abstraction has led to the development of synthesis and simulation technologies. The methodology in common practice today is to design, simulate, and synthesize
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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