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54_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

54_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Introduction 23 (b) ab c a b f c f = ab + bc 1 0 × 1 1 11x x10 01x x00 10x x01 {111,101,010,000} Test Vectors (a) ab c f = abc + abc 111 010 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 × 1 1 011 110 101 000 110 011 {111,110,101,011,010,000} f SA1 b c a SA1 SA1 SA1 FIGURE 1.11 Example of different implementations and their test vectors. set of test vectors for Figure 1.11b is a subset of those required for Figure 1.11a and, as a result, would not detect the four SA1 faults shown in the gate-level implementation of Figure 1.11a. This example can also be illustrated by considering Theorems 1.1 and 1.2. If ATPG assumes that a combinational logic circuit will be fanout free based on the functional description, it could produce test vectors to detect stuck-at faults for all primary inputs based on Theorem 1.1. Yet, if the synthesized circuit contains fanout stems, the set of test vectors produced by the APTG may not detect stuck-at faults on all fanout branches and, as a result of Theorem 1.2, may not detect all stuck-at faults in the circuit. Note that the four SA1 faults in Figure 1.11a not detected by the test vectors in Figure 1.11b are
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