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28 VLSI Test Principles and Architectures coverage in reasonable computational time and cost unless DFT techniques are adopted [Breuer 1987]. 1.5.3 Fault Simulation A fault simulator emulates the target faults in a circuit in order to determine which faults are detected by a given set of test vectors. Because there are many faults to emulate for fault detection analysis, fault simulation time is much greater than that required for design verification. To accelerate the fault simulation process, improved approaches have been developed in the following order. Parallel fault simulation uses bit-parallelism of logical operations in a digital computer. Thus, for a 32-bit machine, 31 faults are simulated simultaneously. Deductive fault simulation deduces all signal values in each faulty circuit from the fault-free circuit values and the circuit structure in a single pass of true-value simulation augmented with the deductive procedure. Concurrent fault simulation is essentially an event- driven simulation to emulate faults in a circuit in the most efficient way. Hardware
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This note was uploaded on 05/16/2011 for the course ENGINEERIN mp108 taught by Professor Elbarki during the Spring '08 term at Alexandria University.

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