60_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES

60_pdfsam_VLSI TEST PRINCIPLES & ARCHITECTURES -...

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Introduction 29 large for current, complex VLSI devices due to the collective leakage currents of millions of transistors on a chip. This makes the detection of the additional I DDQ current due to a single faulty transistor or bridging fault difficult; hence, I DDQ testing is becoming ineffective. A similar approach is transient power supply current (I DDT ) testing. When a CMOS circuit switches states, a momentary path is established between the sup- ply lines V DD and V SS that results in a dynamic current I DDT . The I DDT waveform exhibits a spike every time the circuit switches with the magnitude and frequency components of the waveform dependent on the switching activity; therefore, it is possible to differentiate between fault-free and faulty circuits by observing either the magnitude or the frequency spectrum of I DDT waveforms. Monitoring the I DDT of a CMOS circuit may also provide additional diagnostic information about pos- sible defects unmatched by I DDQ and other test techniques [Min 1998]; however,
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