Unformatted text preview: most important, DFT technique proposed [Eichelberger 1977]. LSSD is latch based. In a flip-flop-based scan design, testability is improved by adding extra logic to each flip-flop in the circuit to form a shift register, or scan chain, as illustrated in Figure 1.13. During the scan mode, the scan chain is used to shift in (or scan in) a (a) controllability test point (b) observability test point Primary output Normal system data Internal node to be observed Test mode select 1 Internal node to be controlled Test data input Test mode select 0 1 Normal system data ± FIGURE 1.12 Ad hoc DFT test points using multiplexers. FFs Combinational Logic Inputs Primary Outputs FF D i Clk Q i FFs Combinational Logic Primary Outputs Scan Data In Scan Data Out FF Clk D i Q i –1 Scan Mode 1 Q i Primary Inputs Primary ± FIGURE 1.13 Transforming a sequential circuit for scan design....
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- Spring '08
- DFT, Flip-flop, Automatic test pattern generation, Design For Test