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30 VLSI Test Principles and Architectures controllability and observability were first defined in the 1970s [Goldstein 1979] to help find those parts of a digital circuit that will be most difficult to test and to assist in test pattern generation for fault detection. Many DFT techniques have been proposed since that time [McCluskey 1986]. DFT techniques generally fall into one of the following three categories: (1) ad hoc DFT techniques, (2) level-sensitive scan design (LSSD) or scan design ,or(3) built-in self-test (BIST). Ad hoc methods were the first DFT techniques introduced in the 1970s. The goal was to target only those portions of the circuit that would be difficult to test and to add circuitry to improve the controllability or observability. Ad hoc techniques typically use test point insertion to access internal nodes directly. An example of a test point is a multiplexer inserted to control or observe an internal node, as illustrated in Figure 1.12. Level-sensitive scan design, also referred to as scan design, was the next, and
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Unformatted text preview: most important, DFT technique proposed [Eichelberger 1977]. LSSD is latch based. In a flip-flop-based scan design, testability is improved by adding extra logic to each flip-flop in the circuit to form a shift register, or scan chain, as illustrated in Figure 1.13. During the scan mode, the scan chain is used to shift in (or scan in) a (a) controllability test point (b) observability test point Primary output Normal system data Internal node to be observed Test mode select 1 Internal node to be controlled Test data input Test mode select 0 1 Normal system data ± FIGURE 1.12 Ad hoc DFT test points using multiplexers. FFs Combinational Logic Inputs Primary Outputs FF D i Clk Q i FFs Combinational Logic Primary Outputs Scan Data In Scan Data Out FF Clk D i Q i –1 Scan Mode 1 Q i Primary Inputs Primary ± FIGURE 1.13 Transforming a sequential circuit for scan design....
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