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Introduction 31 test vector to be applied to the combinational logic. During one clock cycle in the system mode of operation, the test vector is applied to the combinational logic and the output responses are clocked into the flip-flops. The scan chain is then used in the scan mode to shift out (or scan out) the combinational logic output response to the test vector while shifting in the next test vector to be applied. As a result, LSSD reduces the problem of testing sequential logic to that of testing combinational logic and thereby facilitates the use of ATPG developed for combinational logic. Built-in self-test was proposed around 1980 [Bardell 1982] [Stroud 2002] to inte- grate a test-pattern generator (TPG) and an output response analyzer (ORA) in the VLSI device to perform testing internal to the IC, as illustrated in Figure 1.14. Because the test circuitry resides with the CUT, BIST can be used at all levels of testing, from wafer through system-level testing.
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