Introduction31test vector to be applied to the combinational logic. During one clock cycle in thesystem mode of operation, the test vector is applied to the combinational logic andthe output responses are clocked into the flip-flops. The scan chain is then used inthe scan mode to shift out (or scan out) the combinational logic output response tothe test vector while shifting in the next test vector to be applied. As a result, LSSDreduces the problem of testing sequential logic to that of testing combinationallogic and thereby facilitates the use of ATPG developed for combinational logic.Built-in self-test was proposed around 1980 [Bardell 1982] [Stroud 2002] to inte-grate atest-pattern generator(TPG) and anoutput response analyzer(ORA) inthe VLSI device to perform testing internal to the IC, as illustrated in Figure 1.14.Because the test circuitry resides with the CUT, BIST can be used at all levels oftesting, from wafer through system-level testing.
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